One type of integrated circuit reliability problem known in the art is soft errors (James F. Ziegler, “SER—History, Trends and Challenges. A Guide for Designing with Memory ICs”). Soft errors occur when digital information spontaneously changes due to radiation effects. Soft errors do not permanently damage hardware but rather corrupt electronically stored information, which can lead to circuit failure. Other terms typically used to describe this reliability problem are “Single-Event Upset” (SEU) and “Single-Event Effects” (SEE). The rate at which soft errors occur is known as the soft error rate (SER).
The radiation that causes soft errors to occur has three primary sources: (1) thermal neutrons; (2) alpha particles generated from contaminants in CMOS processing or packaging; and (3) high-energy neutrons. High energy neutrons tend to be the most problematic radiation source as they are difficult to absorb by packaging techniques, and following a nuclear reaction between the incident neutron and a silicon atom in the substrate, secondary ions are produced that generate approximately ten times as much free charge compared to the charge generated from an alpha particle strike (Kenichi Osada et al., “Analysis of SRAM Neutron-Induced Errors Based on the Consideration of Both Charge-Collection and Parasitic-Bipolar Failure Modes,” IEEE 2004 Custom Integrated Circuits Conference, p. 357).
FIG. 1 illustrates a conventional CMOS structure 100 comprising an NMOS device 101 and a PMOS device 102. The device may be part of a larger cell or integrated circuit such as a 6-T SRAM cell that comprises two cross-coupled CMOS devices, and which is particularly susceptible to soft errors. The NMOS/PMOS devices 101/102 have a gate electrode 105/106 on a gate insulator layer 109, a source electrode 110/111 and a drain electrode 115/116. The gate electrodes 105/106 have a protective sidewall spacer insulator 151. For the illustrative CMOS device of FIG. 1, the source electrode 110 of the NMOS device 101 is connected to ground (GND) 180. The source electrode 111 of the PMOS device 102 is connected to the power supply Vdd 175. The gate electrodes 105,106 are connected to the input voltage Vi 182, which is GND. The drain electrodes 115,116 are connected to the output voltage Vo 185, which is at Vdd, by means of the PMOS device 102 being in the on-state. The NMOS device 101 is in the off-state, which is a state generally susceptible to soft errors.
P-well 120 doping is provided to isolate the NMOS device 101 from other PMOS devices, while N-well 121 doping is provided to isolate the PMOS device 102 from other NMOS devices. The channel doping regions 126,127 are commonly provided by halo or pocket implants. A field oxide 190 electrically isolates devices from one another, the field oxide for example being an STI field oxide. A depletion layer 130 is formed at the p-n diode junction 140 of the drain electrode 115 with the P-well 120. The width of the depletion layer 130 is a function of the drain bias and the doping in the substrate.
For the sake of illustrating the important physics and mechanisms that lead to soft errors, the NMOS device 101 is discussed. Referencing FIG. 1, a high energy alpha particle 150 is shown striking through the drain electrode 115, through the drain depletion layers 130, then through the P-well 120 and further into the semiconductor substrate 145. Along the path of the striking alpha particle 150, electron and hole pairs 155 are created, thereby generating free charge along the strike path 160. The carriers located within a high electric field region such as in the drain depletion region 130 of the drain-substrate p-n diode junction are quickly collected (electrons) or repelled into the substrate (holes). Charge neutrality prevails at the instant the free charge is generated during the strike event. However, as the electrons and holes in the depletion layer 130 distribute themselves relatively quickly vis-à-vis a drift mechanism, charge neutrality does not prevail and the semiconductor bands bend, resulting in a perturbed potential profile 161 in the vicinity of the strike path 160. The potential perturbation progresses along the particle strike path 160 as more and more of the free charge is either swept or funneled towards the drain 115 (electrons) or into the semiconductor substrate 145 (holes) via this rapid drift mechanism. After tens of nanoseconds, the charge sufficiently redistributes so that the carrier density becomes comparable to the substrate doping and the disturbed field along the particle track relaxes to its original state. This highly transient field disruption immediately after the particle strike is commonly referred to as the field-funneling effect (C. M. Hsieh, et al., “A Field-funneling Effect on the Collection of Alpha-Particle-Generated Carriers in Silicon Devices”, IEEE Electron Device Letters, V. 2, no. 4, p. 103, 1981). If the amount of charge collected at the drain 115 during the field-funneling process is larger than a critical charge (Qcrit), the drain 115 voltage can permanently be lowered and a soft error occurs. In the context of a 6-T SRAM cell, this would lead to a “flipped bit” or single-event upset (SEU) of the cell state.
The holes that drift away from the drain 115 due to the field-funnel effect and the balance of the free charge from the particle strike outside of the funnel region proceed to be transported through a diffusion mechanism. In particular, the P-well 120 floats to a positive bias due to the excess hole charge, which, if sufficiently high, activates parasitic bipolar action at the source 110 and potentially between the NMOS device 101 and neighboring devices. In particular, charge amplification occurs at the source 110 while collecting the hole carriers due to significant back injection of electrons caused by parasitic bipolar effect (Osada). The back-injected electrons traverse the channel and are collected at the drain 115, further adding to the drain collected charge and may tip the drain 115 past Qcrit, thereby causing a soft-error, when otherwise an error may not have occurred. Furthermore, the floating P-well 120 activates a parasitic bipolar device between the P-well 120 and the neighboring cell (not shown), which leads to a flow of back-injected electrons from the neighboring cell source to the neighboring cell drain, and therefore a lowering of the voltage on the neighboring cell drain and ultimately a soft error. As a result, multiple bits can flip from a single particle strike, an effect known as “Multi-bit upsets” (MBU) or “Multi-cell errors” (MCE).
Latch-up is unique problem for CMOS circuits and is caused by the presence of lateral bipolar NPN and PNP transistors. These unwanted parasitic bipolar transistors can act as amplifiers, causing the circuit to fail by shorting power to ground. To solve this problem, a conventional CMOS layout typically includes N-type and P-type well implants for the PMOS and NMOS devices respectively. The N-type and P-type well implants are electrically contacted via ohmic contacts to Vdd and ground power supplies respectively. Referencing FIG. 1 as an example, an N-well 121 is doped with the opposite polarity of that of the semiconductor substrate 145. The well fabrication procedure depends on the requirements for latch-up immunity, and other factors such as packing density and independent threshold voltage adjustment. A heavily doped N-type ohmic contact 170 is provided in direct contact with the N-well 121, and is electrically connected to the supply voltage Vdd 175, while the substrate 145 is typically grounded. A related soft error mechanism is “single-event latchup” (SEL), which occurs when latchup is triggered by anomalous charge generated during a particle strike, such as the particle strike 150 illustrated in FIG. 1.
In summary, there are a variety of failure mechanisms that lead to soft errors including for example SEU, MBU, and SEL. In these cases, the failure is generally traceable to one of two mechanisms: the field-funneling effect or parasitic bipolar action activated by well charging. The problem has historically been mitigated but generally not completely eliminated by several means including for example modifying the manufacturing process, altering the CMOS device architecture, adding error correction code to the integrated circuit, adding protective packaging layers and shielding to block radiation, or optimizing the system design. However, these approaches generally do not guarantee elimination of the soft error problem and are used at the expense of added cost, size, weight, and generally decreased speed performance and increased power consumption. Furthermore, as semiconductor technology continues to scale to higher density integration, lower storage node capacitances and reduced voltages, integrated circuits become increasingly sensitive to the radiation effects that cause soft errors. As a result, the problem of soft errors will become an increasingly problematic reliability challenge for integrated circuit manufacturers in the future.
There is a need in the art for a CMOS integrated circuit technology that eliminates soft errors without added cost and performance degradation.